This invention relates to a method for manufacturing semiconductor device and in particular an integrated circuit (IC) device.
A MOS type integrated circuit (hereinafter referred to as MOS IC) of semiconductor devices is greatly required to enhance the degree of integration from the standpoint of price reduction as well as compactness. However, a limitation on the enhanced integration is encountered during a photoengraving step (a technique for selectively removing a masking layer or a metal layer on a substrate surface hereinafter referred to as a PE technique -) in the manufacture of semiconductor devices. A selfalign gate (SAG) process is known as being capable of omitting one PE step. FIGS. 1(a) to 1(f) are cross-sectional views schematically showing the sequence of a SAG step. A Si0.sub.2 film 2 is formed on the surface of a silicon substrate 1 as shown in FIG. 1(a) and the Si0.sub.2 film 2 is selectively removed by the PE technique to leave an opening 3 as shown in FIG. 1(b). After a SiO.sub.2 film 2a for a gate oxide film is covered on the resultant substrate, a polysilicon layer 4 is covered on the SiO.sub.2 film 2 and 2a as shown in FIG. 1(c). The polysilicon layer is selectively removed to leave a gate electrode 4a as shown in FIG. 1(d). After removing those portions of the SiO.sub.2 layer which correspond to source and drain regions to be formed, an impurity is introduced into the substrate to form source and drain regions 5 and 6 as shown in FIG. 1(e). A thin SiO.sub.2 film (not shown) formed on the exposed surfaces of the source and drain regions are removed by the PE technique so as to form electrode contact portions and after coating a metal film on the resultant semiconductor structure, the surface of the semiconductor structure is subjected to patterning to form source and drain electrodes 5a and 6a as shown in FIG. 1(f). As a result, a MOS IC device is manufactured. Since, however, the height of the uneven, superposed layer on the substrate is great as compared with the length of the electrode contact portion as shown in FIG. 1(f), it is difficult to form a fine pattern at the electrode contact portion. That is, the PE step used in the formation of the electrode contact portion often determines the size of semiconductor elements, since it requires a most fine patterning in comparison with the other PE steps. The depth of the uneven, superposed layer on the substrate is usually of the order of about 1.mu. as measured from the substrate as shown in FIG. 1(e) and the length of the electrode contact portion is industrially limited to about 4 to 5.mu..
Since the uneven surface of the semiconductor structure provides a bar to the formation of a subsequent connection metal layer, a LOCOS (local oxide of silicon) process is applied to make the surface of a semiconductor structure even smoother. The LOCOS process will now be explained below by refering to FIGS. 2(a) to (g). A Si.sub.3 N.sub.4 film 12 is coated on the surface portion of a silicon substrate 11 as shown in FIG. 2(a) and the surface of the resultant substrate is chemically etched with the Si.sub.3 N.sub.4 film 12 as a mask as shown in FIG. 2(b) (this is a PE step). The substrate is thermally oxidized to form a SiO.sub.2 film 13 on the exposed surface of the substrate as shown in FIG. 2(c). The Si.sub.3 N.sub.4 film 12 is replaced by a SiO.sub.2 film (part of the SiO.sub.2 film afterward constitutes a gate oxide film) 13a and a doped polysilicon film 14 is covered on the resultant SiO.sub.2 film 13 and 13a as shown in FIG. 2(d). The polysilicon film 14 is selectively removed by a photoengraving method to form a polysilicon area 15 for a gate as shown in FIG. 2(e). After the SiO.sub.2 film 13a is selectively removed from the substrate surface, source and drain regions 16 and 17 are formed by a diffusion method in the surface areas of the substrate as shown in FIG. 2(f) and a contact hole for electrodes is provided by the PE method. A metal layer for electrodes is formed on the resultant semiconductor structure and, after the metal layer is selectively removed, source and drain electrodes 16a and 17a are formed as shown in FIG. 2(g). Although this LOCOS method permits formation of a relatively flat metal connection layer for electrodes as compared with the SAG process as shown in FIG. 1 it is difficult to form a tiny hole, since the poly-Si layer 15 is stepped in configuration.